专利详情

专利名称	Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance
申请号	US201314029157	专利类型	US
公开（公告）号	US8741703(B2)	公开（授权）日	2014.06.03
申请（专利权）人	中国科学院微电子研究所	发明（设计）人	Zhu Huilong
主分类号	H01L21/00	IPC主分类号	H01L21/00
专利有效期	Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance 至Method for manufacturing FinFET with improved short channel effect and reduced parasitic capacitance	法律状态
说明书摘要	The present application discloses a method for manufacturing a semiconductor device. The method may comprise providing a fin in a semiconductor layer of a SOI substrate, and providing a stack of gate dielectric and gate conductor on only a first side of the fin. The gate conductor may extend laterally away from the first side of the fin in a gate extending direction. The method may comprise doping the fin at its other two opposing sides so as to provide a source region and a drain region. Each of the source and drain regions may have a portion extending laterally away from a second side, opposite to the first side, of the fin in a source/drain extending direction. The gate extending direction and the source/drain extending direction can be parallel to the main surface of the SOI substrate, while being opposite to each other. The method may comprise providing a channel region at a central portion of the fin.