专利详情

专利名称	Read timing generation circuit
申请号	US201114123104	专利类型	US
公开（公告）号	US9047935(B2)	公开（授权）日	2015.06.02
申请（专利权）人	中国科学院微电子研究所	发明（设计）人	Chen Weiwei;Chen Lan;Yang Shiyang
主分类号	G11C7/00	IPC主分类号	G11C7/00;G11C7/22;G11C8/18;G11C8/06;G11C7/12
专利有效期	Read timing generation circuit 至Read timing generation circuit	法律状态
说明书摘要	Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit.