专利详情

专利名称	Method for preparing GOI chip structure
申请号	US201213825010	专利类型	US
公开（公告）号	US8877608(B2)	公开（授权）日	2014.11.04
申请（专利权）人	中国科学院上海微系统与信息技术研究所	发明（设计）人	Di Zengfeng;Ye Lin;Xue Zhongying;Zhang Miao
主分类号	H01L21/46	IPC主分类号	H01L21/46;H01L21/762
专利有效期	Method for preparing GOI chip structure 至Method for preparing GOI chip structure	法律状态
说明书摘要	The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.